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19-1873; Rev 0; 12/00
8-Bit CODECs
General Description
The MAX1102/MAX1103/MAX1104 CODECs provide both an 8-bit analog-to-digital converter (ADC) and an 8-bit digital-to-analog converter (DAC) with a 4-wire logic interface. The MAX1102/MAX1103 include an onboard +2V/+4V reference, providing a well-regulated, low noise reference for both the ADC and DAC. The MAX1104 offers ratiometric conversion, with the reference internally connected to VDD. The MAX1102/MAX1103/MAX1104 are low-cost, lowpower CODECs for use with microcontrollers (Cs). They allow for greater flexibility when selecting a C. Less expensive Cs without onboard converters can be used while maintaining overall system performance. The MAX1102 operates from a single +2.7V to +3.6V supply, the MAX1103 operates from a +4.5V to +5.5V supply, and the MAX1104 operates from a +2.7V to +5.5V supply. The MAX1102/MAX1103 incorporate a VDD monitor in addition to AIN for power supply monitoring. All devices feature a low 18A standby mode, where both data converters are disabled while the reference remains active, and three shutdown modes: ADC disabled, DAC disabled, and complete shutdown (1A). A quick 10s wake-up time allows the MAX1102/MAX1103/MAX1104 to cycle in and out of shutdown even during short-duration idle times. The MAX1102/MAX1103/MAX1104 are available in a space-saving 8-pin MAX package.
Features
o 8-Bit ADC 1LSB INL Built-In Track-and-Hold 48dB of SINAD o 8-Bit DAC 1LSB INL 55dB of SFDR o Internal Conversion Clock o Single-Supply Operation +2.7V to +3.6V (MAX1102) +4.5V to +5.5V (MAX1103) +2.7V to +5.5V (MAX1104) o Low Power Consumption 0.5mA at 25ksps 1A Shutdown Mode o 6MHz 4-Wire SPITM, QSPITM, and MICROWIRETM Compatible Interface o Compact 8-Pin MAX Package o Internal Voltage Reference +2V: MAX1102 +4V: MAX1103 o Power-Supply Monitor (MAX1102/MAX1103) o Rail-to-Rail(R) DAC Output Buffer
MAX1102/MAX1103/MAX1104
Ordering Information
PART MAX1102EUA MAX1103EUA MAX1104EUA TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 MAX 8 MAX 8 MAX REFERENCE +2V +4V VDD
________________________Applications
Analog I/O for Microcontrollers Analog System Signal Supervision Voice Recording and Playback
Functional Diagram
VDD
MAX1102 MAX1103 MAX1104
Pin Configuration
TOP VIEW
VDD/2 ADC T/H
CS SCLK DIN DOUT
SERIAL INTERFACE AND CONTROL LOGIC
VOLTAGE REFERENCE DAC LATCH DAC
AIN
VDD GND AIN OUT
1 2 3 4
8
DIN DOUT SCLK CS
AOUT
MAX1102 MAX1103 MAX1104 MAX
7 6 5
GND
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. ________________________________________________________________ Maxim Integrated Products 1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
8-Bit CODECs MAX1102/MAX1103/MAX1104
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V AIN, OUT, DOUT to GND ...........................-0.3V to (VDD + 0.3V) DIN, SCLK, CS to GND ............................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.1mW/C above +70C) .................330mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering,10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER ADC DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) MAX1102/MAX1103 MAX1104 INL DNL All codes Guaranteed monotonic 8 1/4 1/4 1 1 1 5 1 Bits LSB LSB LSB % LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC DYNAMIC SPECIFICATIONS (fAIN = 10kHz SINE WAVE. VAIN = 0.9 VREFp-p) Signal to Noise and Distortion Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Full-Power Bandwidth ADC Wake-Up Time from Standby ADC Wake-Up Time from Full Shutdown ANALOG INPUT Analog Input Voltage Input Resistance Input Capacitance VOLTAGE REFERENCE Reference Voltage Temperature Coefficient CONVERSION RATE Conversion Time Track/Hold Acquisition Time Internal Clock Frequency tCONV tACQ 375 24 36 3.5 s s kHz VREF MAX1102 MAX1103 MAX1102/MAX1103 2 4 100 V ppm/oC VAIN RIN CIN 0 10 20 VREF V M pF Reference enabled (MAX1102/MAX1103) MAX1102/MAX11103 MAX1104 SINAD SFDR THD 48 59 58 2.5 3 200 3 dB dB dB MHz s s
2
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8-Bit CODECs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25C unless otherwise noted.)
PARAMETER Throughput Rate DAC DC ACCURACY Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error MAX1104 DAC DYNAMIC SPECIFICATIONS (fOUT = 1kHz SINE WAVE, VOUT = 0.9 VREFp-p) Spurious-Free Dynamic Range Total Harmonic Distortion Small-Signal Bandwidth Full-Power Bandwidth DAC Wake-Up Time from Standby (Note 4) DAC Wake-Up Time from Full Shutdown (Note 4) DAC OUTPUT Full-Scale Swing Settling Time (Note 5) Slew Rate Load Regulation RL open to 10k 0 < VOUT < VDD - 0.1V VDD 0.7 VDD 0.3 VLOGIC = GND or VDD 0.1 0.5 15 VOH VOL ILEAK ISOURCE = 1.0mA ISINK = 1.0mA VDD 0.9 VDD 0.1 5.0 5 MAX1104 Settle to within 1/2 LSB 0 11 1.2 0.05 VDD 0.1 V s V/s LSB Reference enabled (MAX1102/MAX1103) MAX1102/MAX1103 MAX1104 10 SFDR THD 55 53 1 72 10 200 Gain Error (Note 3) MAX1102/MAX1103 INL DNL Guaranteed monotonic 8 1/4 1/4 1 1 30 5 30 Bits LSB LSB mV % mV dB dB MHz kHz s SYMBOL CONDITIONS ADC in continuous conversion mode MIN 25 TYP MAX UNITS ksps
MAX1102/MAX1103/MAX1104
s
LOGIC INPUTS AND OUTPUTS (DIN, SLCK, CS) Input High Voltage Input Low Voltage Input Current Digital Input Hysteresis Digital Input Capacitance Output High Voltage Output Low Voltage Three-State Leakage VIH VIL V V A V pF V V A
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3
8-Bit CODECs MAX1102/MAX1103/MAX1104
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25C unless otherwise noted.)
PARAMETER SYMBOL MAX1102 Supply Voltage VDD MAX1103 MAX1104 Supply Current Standby Current Full Shutdown Current ICC ADC on (25ksps), DAC off ADC off, DAC on (VDD = +5.5V) ADC off, DAC off, clock off, reference on ADC off, DAC off, clock off CONDITIONS MIN 2.7 4.5 2.7 0.25 0.4 18 1 TYP MAX 3.6 5.5 5.5 0.5 0.66 35 mA A A V UNITS POWER SUPPLY REQUIREMENTS
TIMING CHARACTERISTICS (Figures 4a and 4b)
(VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25C unless otherwise noted.)
PARAMETER Power Up to Reset Complete CS Rise-to-DOUT = High-Z CS Fall-to-DOUT Valid CS Fall-to-SCLK Rise SCLK Fall-to-CS Rise DIN-to-SCLK Setup Time DIN-to-SCLK Hold Time SCLK Fall to DOUT Valid SCLK Maximum Frequency SCLK Pulse Width High SCLK Pulse Width Low SYMBOL t9 t10 t11 t3 t8 t4 t5 t6 fSCLK tCH tCL 60 70 RDOUT = 3k, CDOUT = 50pF RDOUT = 3k, CDOUT = 50pF 15 25 10 15 70 6 CONDITIONS MIN TYP 40 40 60 MAX UNITS s ns ns ns ns ns ns ns MHz ns ns
Note 1: MAX1102/MAX1104 tested with VDD = +3V. MAX1103 tested with VDD = +5V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Gain error calculation is referenced to the ideal FS output. Gain error for the MAX1102/MAX1103 also includes reference initial accuracy error. Note 4: Wake-up time is the time it takes for the DAC output to settle to within 1/2 LSB of the FS value after a power-up command. Note 5: Output settling time is measured by taking the DAC from code 00hex to FFhex.
4
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8-Bit CODECs
Typical Operating Characteristics
(VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (ADC ENABLED, DAC DISABLED)
MAX1102 toc01
MAX1102/MAX1103/MAX1104
SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC ENABLED, ADC DISABLED)
MAX1102 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (ADC ENABLED, DAC ENABLED)
450 400 SUPPLY CURRENT (A) 350 300 250 200 150 100 50 0 ADC CODE = AAhex 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DAC CODE = 00hex DAC CODE = FFhex
MAX1102 toc03
300 250 SUPPLY CURRENT (A) 200 150 100 50 0 2.5
CODE = AAhex
350 300 SUPPLY CURRENT (A) 250 200 CODE = 00hex 150 100 50 0 CODE = FFhex
500
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1102 toc04
ADC OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1102 toc05
DAC OFFSET ERROR vs. SUPPLY VOLTAGE
CODE = 0Ahex
MAX1102 toc06
20
5.0 4.5 4.0 OFFSET ERROR (mV) 3.5 3.0 2.5 2.0 1.5 1.0
10
SUPPLY CURRENT (A)
OFFSET ERROR (mV) 2.5 3.0 3.5 4.0 4.5 5.0 5.5
15
ADC and DAC OFF REFERENCE ON
9
8
10
7
5 ADC, DAC, and REFERENCE OFF 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
6
0.5 0 SUPPLY VOLTAGE (V) 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
ADC GAIN ERROR vs. SUPPLY VOLTAGE
MAX1102 toc07
ADC GAIN ERROR vs. TEMPERATURE
MAX1102 toc08
DAC GAIN ERROR vs. SUPPLY VOLTAGE
9 8 GAIN ERROR (mV) 7 6 5 4 3 2 1 0 VREF = 2.0V CODE = FFhex
MAX1102 toc09
2.00 1.75 1.50 GAIN ERROR (%FS) 1.25 1.00 0.75 0.50 0.25 0 2.5
10 9 8 GAIN ERROR (mV) 7 6 5 4 3 2 1 0 VREF = 2.0V CODE = 7Fhex
10
VREF = 2.0V CODE = FFhex
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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5
8-Bit CODECs MAX1102/MAX1103/MAX1104
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = +25C, unless otherwise noted.)
DAC OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT
MAX1102 toc10
DAC GAIN ERROR vs. TEMPERATURE
20 VDD = +5.0V VREF = +2.0V CODE = FFhex 1600 1400 OUTPUT VOLTAGE (mV) 1200 1000 800 600 400 200 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0
DAC OUTPUT HIGH VOLTAGE vs. OUTPUT SOURCE CURRENT
3.90 CODE = FFhex OUTPUT VOLTAGE (V) 3.85 3.80 3.75 3.70 3.65 3.60 3.55 0 VDD = +5.0V VREF = +4.0V 2 4 6 8 10 CODE = F0hex
MAX1102 toc12
VDD = +5.0V CODE = 00hex
15 GAIN ERROR (mV)
10
CODE = 0Ahex
5
0
2
4
6
8
10
MAX1102 toc11
3.95
OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
ADC INTEGRAL NONLINEARITY vs. CODE
MAX1102 toc13
ADC DIFFERENTIAL NONLINEARITY vs. CODE
MAX1102 toc14
DAC INTEGRAL NONLINEARITY vs. CODE
0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00
MAX1102 toc15
1.00 INTERGRAL NONLINEARITY (LSB) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 50 100 150 200 250
1.00 DIFFERENTIAL NONLINEARITY (LSB) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 50 100 150 200 250
1.00 INTERGRAL NONLINEARITY (LSB)
300
300
0
50
100
150
200
250
300
ADC OUTPUT CODE
ADC OUTPUT CODE
DAC OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY vs. CODE
MAX1102 toc16
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
MAX1102 toc17
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
MAX1102 toc18
1.00 DIFFERENTIAL NONLINEARITY (LSB) 0.75 0.50 0.25 0 -0.25
3V SCLK 0 SCLK
3V
0
OUT -0.50 -0.75 -1.00 0 50 100 150 200 250 300 1s/div 1s/div DAC OUTPUT CODE OUT 20mV/div 20mV/div
6
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8-Bit CODECs
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k, COUT = 100pF, TA = +25C, unless otherwise noted.)
MAX1102/MAX1103/MAX1104
POSITIVE SETTLING TIME
MAX1102 toc19
NEGATIVE SETTLING TIME
MAX1102 toc20
CLOCK FEEDTHROUGH
MAX1102 toc21
3V SCLK 0 SCLK
3V SCLK 0
3V 0
OUT 1V/div
OUT 1V/div
OUT 2mV/div
1s/div
1s/div
1s/div
ADC FFT
MAX1102 toc22
DAC FFT
VDD = +4.5V 20 0 MAGNITUDE (dB) -20 -40 -60 -80 -100 -120 0 1 2 3 4 5 6 7 8 9 10
MAX1102 toc23
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 0
40
VDD = +4.5V FSAMPLE = 24.576kHz FL = 10.002kHz
2
4
6
8
10
12
14
FREQUENCY (kHz)
FREQUENCY (kHz)
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7
8-Bit CODECs MAX1102/MAX1103/MAX1104
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME VDD GND AIN OUT CS SCLK DOUT DIN Voltage Supply Ground ADC Analog Input DAC Analog Voltage Output Chip Select Input. Device ignores all logic signals when CS is high. Serial Clock Input. Data in is latched on the rising edge, data out transitions on the falling edge. ADC Digital Output. Output is high impedance when CS is high. DAC Digital Input. Input ignores all signals when CS is high. FUNCTION
Detailed Description
The MAX1102/MAX1103/MAX1104 are 8-bit CODECs in a compact 8-pin package. These devices consist of an 8-bit ADC, an 8-bit DAC, track/hold (T/H), DAC output buffer amplifier, internal voltage reference, input multiplexer (mux) and a 6MHz SPI, QSPI and MICROWIRE compatible 4-wire serial interface. A single 8-bit word configures the MAX1102/MAX1103/MAX1104, providing a simple interface to a microcontroller (C).
shows the detailed functional diagram of the ADC block. ADC Operation The input architecture of the ADC is illustrated in Figure 2, the equivalent input circuit, and is composed of the T/H, input mux (MAX1102/MAX1103), input comparator, switched capacitor DAC, and the auto-zero rail. The switched capacitor DAC is independent of the R-2R ladder DAC and does not provide the converted analog output on OUT. The T/H is in hold mode while a conversion is taking place. Once the conversion is completed, the T/H enters acquisition mode, and tracks the input signal until the start of the next conversion. In single conversion mode, conversion starts at the falling clock edge corresponding to the last bit of the control word. In continuous conversion mode, the first conversion following the control word starts on the falling clock edge of the
Analog-to-Digital Converter
The MAX1102/MAX1103/MAX1104 ADC section uses a successive-approximation (SAR) conversion technique and input T/H circuitry to convert an analog signal to an 8-bit digital output. No external hold capacitors are required. The MAX1102/MAX1103 have an input multiplexer that directs either AIN or VDD/2 to the input of the T/H, allowing these devices to either convert the analog input, or monitor the power supply. Figure 1
CS SCLK DIN CONTROL LOGIC/2
INTERNAL OSCILLATOR
MAX1102 MAX1103
AIN VDD/2
ANALOG INPUT MUX
T/H
SUCCESSIVE APPROXIMATION REGISTER CHARGE REDISTRIBUTION DAC
ANALOG OUTPUT INPUT SHIFT MUX REGISTER
DOUT
INTERNAL OSCILLATOR
Figure 1. ADC Detailed Functional Diagram 8 _______________________________________________________________________________________
8-Bit CODECs
LSB of the control word. Successive conversions are initiated after the last bit of the previous conversion result has been clocked out. Resultant data is only available after conversion is complete. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. This time, tACQ2, is calculated by the following equation: tACQ2 = (6.2 RS 15pF) + tACQ where RS = the source impedance of the input signal; t ACQ is the T/H acquisition time from the Electrical Characteristics table. Conversion Progress The comparator's negative input is connected to the auto-zero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have no voltage difference at the comparator inputs within the limits of an 8-bit resolution. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and GND allow AIN to swing from (GND - 0.3V) to (V DD + 0.3V) without damaging the device. However, for accurate conversions, the input must not exceed (VDD + 0.05V) or be less than (GND - 0.05V). The valid input range for the analog input is from GND to VREF. The output code is invalid (code zero) when a negative input voltage is applied, and full scale (FS) when the input voltage exceeds the reference. Input Bandwidth The ADC's input tracking circuitry has a 2.5MHz fullpower bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, low-pass filters such as the MAX7418- MAX7426 are recommended.
MAX1102/MAX1103/MAX1104
VREF
GND MAX1102 MAX1103 MAX1104
HOLD AIN TRACK 5pF 15pF ZERO CAPACITIVE DAC HOLD
TRACK
Digital-to-Analog Converter
The MAX1102/MAX1103/MAX1104 DAC section uses an R-2R ladder network that converts the 8-bit digital input into an equivalent analog output voltage proportional to the applied reference voltage (Figure 3). The DAC features a double-buffered input, and a buffered analog output.
VDD/2
Figure 2. Equivalent Input Circuit
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
REF GND LSB DAC_ REGISTER NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FFhex. MSB
OUT
Figure 3. DAC Simplified Circuit Diagram _______________________________________________________________________________________ 9
8-Bit CODECs MAX1102/MAX1103/MAX1104
Output Buffer The MAX1102/MAX1103/MAX1104 analog output is internally buffered by a precision unity-gain buffer that slews at 1.2V/s (typ). The output swings from GND to VDD - 0.1V. With a 0 to VDD - 0.1V (or VDD - 0.1V to 0) output transition, the amplifier output typically settles to 1/2LSB in 11s when loaded with 10k in parallel with 100pF. The buffer amplifier is stable with any combination of resistive ( 10k) or capacitive ( 100pF) loads.
AOUT
ADC CONVERSION CYCLE (ADC PREVIOUSLY ENABLED. DAC DISABLED)
CS
t3
SCLK
t11
t3
tconv D7 D6 D5 D4 D3 D2 D1
t10
DOUT
D0 LSB
t4
DIN
MSB D5 t5 D4 D3 D2 D1 D0
CONVERSION RESULT
D7
D6
AIN
MSB
CONTROL WORD
LSB
input sampling instant
Figure 4a. Serial Interface Timing Diagram. ADC enabled and DAC disabled.
VDD
AOUT twake-up tsettling
CS t3 SCLK t3
DOUT t4 DIN D7 D6 D5 t5 MSB CONTROL WORD LSB MSB DAC DATA LSB D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4b. Serial Interface Timing Diagram. ADC disabled and DAC disabled. 10 ______________________________________________________________________________________
8-Bit CODECs
Serial Interface and Control Logic
The MAX1102/MAX1103/MAX1104 have 4-wire serial interfaces (Figure 4). The CS, SCLK, and DIN inputs are used to control and configure the device, while the three-state DOUT provides access to the ADC conversion result. DIN also serves as the data input to the DAC. The serial interface provides easy connection to Cs with SPI, QSPI, and MICROWIRE serial interfaces at clock rates up to 6MHz. For SPI and QSPI, set CPOL = CPHA = 0 in the SPI control registers of the C. Figure 4 gives detailed timing information. Digital Inputs and Outputs The logic levels of the MAX1102/MAX1103/MAX1104 digital inputs are set to accept voltage levels from both +3V and +5V systems regardless of the supply voltages. The control word sets the mode in which the MAX1102/MAX1103/MAX1104 operate. The enable bits, E0 to E2, determine what sections of the device are operating by either enabling or shutting down the two converters and voltage reference (see Shutdown Modes). The enable bits are independent of the address bits; for example, the ADC need not be addressed for it to be shutdown or powered up. C0 and C1 are the control bits. C0 sets the conversion mode, either single or continuous (see Conversion Modes). C1 determines whether the ADC monitors VDD/2 or AIN (see Power Sense). When changing C1, two control words must be written. The first control word changes the state of the mux. Then wait 3.5s for the T/H to acquire the new input. Finally, the second control word causes the conversion to take place. For MAX1104 set C1 = 0. A0 is the ADC address bit. A logic "1" on A0 addresses the ADC. The control word configures the ADC. A logic "0" on A0 deselects the ADC. In this state, the ADC is still active, but does not perform any conversions. A1 is the DAC address bit. A logic "1" on A1 addresses the DAC. The control word configures the DAC, and the eight bits following the control word are read in as DAC data. The converted analog output is available after the eighth data bit is read into the device. A logic "0" deselects the DAC. In this state the DAC is still active, but ignores any digital inputs.
MAX1102/MAX1103/MAX1104
Performing a Conversion
Configuring the MAX1102/MAX1103/MAX1104 The MAX1102/MAX1103/MAX1104 must be configured before a conversion can occur. Following CS falling, on each rising edge of SCLK, a bit from DIN is clocked into the MAX1102/MAX1103/MAX1104's internal shift register. After CS falls, the first arriving logic "1" bit defines the MSB of the control byte (START). Until the START bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 1 shows the control-byte format.
Table 1. Control-Byte Format
BIT 7 (MSB) 6 NAME START A1 DESCRIPTION 1 = designates a new control word. 0 = control word ignored, unless byte is DAC data. 1 = DAC addressed. Current byte configures DAC, the following byte is DAC data. 0 = DAC not addressed. 1 = ADC addressed. Current byte configures ADC. After the 36s conversion time, the next eight clock cycles clock out the conversion result. 0 = ADC not addressed. 1 = ADC input to VDD/2. 0 = ADC input to AIN. 1 = Continuous conversion. Control word not required unless the device is reconfigured. 0 = Single conversion. New control word required before next conversion. 1 = Reference enabled. 0 = Reference disabled. Don't care for MAX1104. 1 = ADC enabled. 0 = ADC disabled. 1 = DAC enabled. 0 = DAC disabled.
5
A0
4 3 2 1 0
C1* C0 E2 E1 E0
* Leave C1 = 0 for MAX1104.
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11
8-Bit CODECs MAX1102/MAX1103/MAX1104
Both the ADC and DAC can be addressed from the same control word, allowing both converters to operate simultaneously. Configuring the ADC When configuring the ADC immediately following power-up, the first control word enables the ADC and sets the T/H to track mode. Then wait 200s for the internal reference to stablize (3s typical from standby mode). Finally, the second control word sets the ADC into either single or continuous mode and causes conversion to take place. Conversion Modes The MAX1102/MAX1103/MAX1104 have two conversion modes, single and continuous. In single conversion mode (C0 = 0), a control word must be written before an ADC conversion result can be read, or DAC input data is accepted. Once a conversion has occurred, the device will ignore any input until a new control word is written. Figures 5 and 6 show the DAC and ADC single conversion mode timing diagrams. In continuous conversion mode (C0 = 1), the device maintains its configuration from a single control word, and continuously updates the ADC conversion result, or accepts new DAC input data. When operating the ADC and DAC simultaneously, both converters must be in the same conversion mode. ADC Single Conversion Mode Set C0 = 0 to select single conversion mode. The falling edge of SCLK after the eighth bit of each control word causes the ADC to switch from track to hold mode and begin conversion. To avoid corruption of the conversion result, SCLK must be disabled for 36s (Figure 6). After completing the conversion, the ADC
CS
SCLK
DIN
DAC S ADDR DAC ON
DAC DATA
DAC S ADDR DAC ON
DAC DATA
DAC S ADDR DAC ON
DAC DATA
DAC S ADDR DAC OFF
DAC DATA
DAC S ADDR DAC ON
DAC DATA
OUT NOTE: "S" DENOTES THE BEGINNING OF A CONTROL WORD
Figure 5. DAC Single Conversion Mode Timing Diagram
CS
SCLK
DIN
S
ADC ON
ADC S ADDR ADC ON tCONV 1
ADC S ADDR ADC ON tCONV 2 ACQUISITION MODE
ADC S ADDR ADC OFF
S
ADC ON
ADC S ADDR ADC ON
ADC S ADDR ADC ON
AIN
3 ACQUISITION MODE MSB LSB CONVERSION RESULT FOR 2 ACQUISITION MODE
4
DOUT
MSB LSB CONVERSION RESULT FOR 1
MSB LSB
MSB LSB
CONVERSION CONVERSION RESULT FOR 3 RESULT FOR 4
Figure 6. ADC Single Conversion Mode Timing Diagram
12
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8-Bit CODECs MAX1102/MAX1103/MAX1104
CS
SCLK
DIN
DAC S ADDR DAC OFF
DAC DATA
DAC DATA
DAC DATA
DAC S ADDR DAC ON
DAC DATA
DAC DATA
DAC DATA
DAC DATA
DAC DATA
OUT
Figure 7. DAC Continuous Conversion Mode Timing Diagram
CS
SCLK
DIN
S ADC ON
ADC S ADDR ADC ON 1 2 tCONV 3
ADC S ADDR ADC ON
S ADC ON
ADC S ADDR ADC ON
AIN T/MIN ACQUISITION MODE DOUT MSB LSB MSB LSB
4 5 6 7
MSB LSB CONVERSION RESULT FOR 3
MSB LSB CONVERSION RESULT FOR 4
MSB LSB CONVERSION RESULT FOR 5
MSB LSB CONVERSION RESULT FOR 6
CONVERSION CONVERSION RESULT FOR 1 RESULT FOR 2
Figure 8. ADC Continuous Conversion Mode Timing Diagram
automatically returns to track mode, and the next eight clock cycles shift out the result on DOUT. A minimum of 3.5s in track mode is required for complete acquisition. DAC Continuous Conversion Mode Once the DAC is configured in continuous conversion mode, the analog output, OUT, is updated at the rising edge of every eighth clock pulse (Figure 7). To exit DAC continuous conversion mode, toggle CS. The device requires a new control word before any further conversions take place. ADC Continuous Conversion Mode Set C0 = 1 to select continuous conversion mode. The falling edge of SCLK after the eighth bit of the control word causes the ADC to switch from track to hold mode and begin conversion. To avoid corruption of the conversion result, SCLK must be disabled for 36s (Figure 8). After completing the conversion, the ADC
OUTPUT CODE 11111111 11111110 11111101
FULL-SCALE TRANSITION
00000011 00000010 00000001 00000000 0 (IN-) 0.5 1.5 2.5 INPUT VOLTAGE (LSB) FS FS - 1.5LSB
Figure 9. ADC Input/Output Transfer Function ______________________________________________________________________________________ 13
8-Bit CODECs MAX1102/MAX1103/MAX1104
automatically returns to track mode, and the next eight clock cycles shift out the result on DOUT. The falling edge of SCLK during the eighth bit of the result will again cause the ADC to switch from track to hold mode and begin the next conversion. A minimum of 3.5s in track mode is required for complete acquisition. In continuous ADC-only conversion mode, a new control word (START = 1) reconfigures the device. ing the input multiplexer, two control words must be written before any conversion takes place. The first control word changes the multiplexer state, and the second starts the conversion.
Reference
The full-scale range of both the ADC and DAC is set by the internal voltage reference. The MAX1102 provides a +2.0V reference, the MAX1103 has a +4.0V reference, and the MAX1104 uses VDD as the reference voltage.
Interrupted Communication Results
If CS transitions from low to high during the reception of a control word, the MAX1102/MAX1103/MAX1104 enters its power-on reset state (full shutdown mode). If CS is toggled while receiving DAC data, the input is ignored and any received bits are discarded. In both cases, once CS returns low, the device requires a new control word before further conversions can occur. If CS goes high while data is read from the device, DOUT enters a high-impedance state, and the serial clock is ignored. When CS returns low, the remaining bits of the conversion result can be clocked out.
ADC Transfer Function
Figure 9 depicts the ADC input/output transfer function. Code transitions occur at the center of every LSB step. Output coding is binary; with a 2.0V reference 1LSB = (VREF/256) = 7.8125mV. Full scale is achieved at VAIN = VREF - 1.5LSB. Negative input voltages are invalid and give a zero output code. Voltages greater than full scale give an all ones output code.
Shutdown Modes
The MAX1102/MAX1103/MAX1104 feature four software-selectable shutdown modes, helping to conserve power by disabling any unused portion of the device. Bits 0 through 2 of the control word select the device shutdown mode (Table 1). Table 2 details the four power modes with the corresponding supply current and operating sections. The ADC and DAC are individually controlled and can be shutdown independently of each other. Bit 0 (E0) controls the DAC, a logic "1" enables the DAC, a logic "0" disables the DAC. Bit 1 (E1) controls the ADC, a logic "1" enables the ADC, a logic "0" disables the ADC. Either the ADC or DAC or both can be shutdown, conserving power when one or both converters are not in use. A fast wake-up time (3s ADC, 10s DAC) allows the converters to be cycled in and out of shutdown even during short duration idle times.
Applications Information
Power-On Reset
When power is first applied, the device enters full shutdown mode and the DAC registers are reset to 0. To wake up the device, the proper control word must be written and 200s allowed for the internal reference to stablize. DAC data may be written to the device immediately following the control word, but OUT will not finish settling until the wake-up time has passed.
Power Sense
The MAX1102/MAX1103 provide a multiplexer which sets the T/H to either AIN or one-half of VDD. With C1 = 1, the ADC converts the V DD /2 voltage, providing power sensing capability to the system. When switch-
Table 2. Operation Modes
BIT E2 0 1 1 1 1 E1 0 0 1 0 1 E0 0 0 0 1 1 1A 18A 250A 400A 520A SUPPLY CURRENT REF Off On On On On OPERATING SECTIONS ADC Off Off On Off On DAC Off Off Off On On
14
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8-Bit CODECs
Power Supply Bypassing and Layout
SYSTEM POWER SUPPLIES GND
MAX1102/MAX1103/MAX1104
+3V/+5V
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the device. Figure 10 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the device ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point. The ground return to the power supply for the star ground should be connected to this point. The ground return to the power supply for the star ground should be low impedance and as short as possible for noisefree operation. High-frequency noise in the VDD power supply may affect device performance. Bypass the supply to the star ground with 0.1F and 1F capacitors close to the device. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10 resistor in series with VDD to form a lowpass filter.
1F
10
0.1F GND VDD DGND VDD
MAX1102 MAX1103 MAX1104
DIGITAL CIRCUITRY
Figure 10. Power-Supply Connections
Data can be written to the DAC while it is in shutdown. A control word with A1 = 1 and E0 = 0 disables the DAC while allowing data to be written to the DAC. The eight bits following this control word are shifted into the DAC register. Conversion takes place once the DAC is enabled. Two control words are necessary to enable the ADC. The first control word brings the ADC out of shutdown, and sets the T/H in acquisition mode. The second control word initiates the conversion. Bit 2 (E2) controls the reference. A logic "1" enables the reference, a logic "0" disables the reference, further reducing power consumption.
Chip Information
TRANSISTOR COUNT: 3226 PROCESS: BiCMOS
______________________________________________________________________________________
15
8-Bit CODECs MAX1102/MAX1103/MAX1104
________________________________________________________ Package Information
8LUMAXD.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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